M.2 E Key vs B+M Key WiFi Modules: Full Comparison

Blog 2026-05-12

Key Overview

M.2 E Key (Socket 1, notch pins 24–31, 60 active pins, 22×30 mm 2230 form factor) is the PCI-SIG-standardized interface for modern Wi-Fi/Bluetooth combo modules. It carries one PCI Express Gen 3 x1 lane (8 GT/s, 984 MB/s), a mandatory USB 2.0 differential pair on pins 3/5 for Bluetooth HCI transport, and optional Intel CNVi on pins 9–23/59–73 for CRF modules. M.2 B+M Key (Socket 2, dual notch at pins 12–19 and 58–65, 67 active pins, 2242/2280 form factor) is specified for SATA and PCIe x2 NVMe storage — not for Wi-Fi. The B+M Key electrical interface lacks mandated USB routing for Bluetooth, uses a host-interface detection mechanism via CONFIG[3:0] pins (pins 1/21/69/75) that identifies SATA, PCIe, or WWAN protocol configuration, and supports no CNVi. Physically, an E Key module cannot enter a B+M slot due to notch collision at pins 24–31; a B+M module cannot seat in an E Key slot due to continuous pin contact at the same region. Over 95% of M.2 Wi-Fi 6/6E/7 modules (Intel AX210/BE200/BE201, Qualcomm QCNCM865, MediaTek MT7925) ship as E Key 2230. B+M Key Wi-Fi modules are limited to legacy Wi-Fi 5 (Broadcom BCM94352Z, Intel 3165) and are end-of-life.

For a complete guide to WiFi module form factors and interfaces, see our WiFi module complete guide.

For an industrial perspective on MiniPCIe vs M.2 form factors — covering mechanical retention, vibration resistance, thermal performance, and lifecycle planning — see our MiniPCIe vs M.2 WiFi Modules: Which is Better for Industrial?.

M.2 E Key vs B+M Key WiFi Modules: Full Comparison

M.2 Interface Standard & Key Notch Basics

The M.2 interface, originally designated Next Generation Form Factor (NGFF), was standardized by PCI-SIG in the PCI Express M.2 Specification Revision 3.0, Version 1.2 (released June 26, 2019). The connector uses a 75-position, 0.5 mm pitch edge-card socket with dual-row contacts on 0.5 mm stagger. Keying is implemented by removing specific contact positions from the module’s edge connector and inserting matching plastic barriers into the corresponding socket positions. This mechanical interlock prevents insertion of a module into a socket whose signal assignment does not match the module’s protocol requirements.

Twelve key types (A through M) are defined in the specification. Each key corresponds to a specific notch position on the 75-position pin field. The three sockets relevant to this comparison are Socket 1 (Key A, Key E, Key A+E — wireless and connectivity), Socket 2 (Key B, Key B+M — storage and WWAN), and Socket 3 (Key M — high-performance NVMe storage). Socket 1 uses PCIe REFCLK0 on pins 47/49, PERST0# on pin 52, CLKREQ0# on pin 53, and PEWAKE0# on pin 55 for the PCIe root port interface. Socket 2 uses its own PERST#, CLKREQ#, and PEWAKE# signals on pins 50, 52, and 54 respectively, and adds the CONFIG[3:0] pins for host interface detection.

The notch is not merely a physical key — it serves as a signal assignment mask. Pins that fall within the notched region are physically absent from the module’s edge connector, which means the corresponding signals on the host side are left unconnected. An E Key module (notch 24–31) physically removes pins 24 through 31 from its edge. A B+M Key module (notch 12–19 + 58–65) removes two separate pin groups. Because the remaining pin assignments differ, no direct signal compatibility exists between the two key types even if an adapter could solve the mechanical mismatch — the PCIe lane mapping, reference clock routing, and sideband signal allocation are fundamentally different.

What Is M.2 E Key WiFi Module

M.2 E Key (Socket 1 per PCI-SIG) occupies edge positions 1 through 75 with a key notch at pins 24–31, yielding 60 electrically active pins. The standard module form factor is 2230 (22 mm width, 30 mm length), with a single-sided component height maximum of 1.5 mm top side and 0.1 mm bottom side per the Intel AX210 product brief. Intel also defines a 1216 (12 mm × 16 mm) soldered-down variant, but 2230 is universal across consumer and industrial platforms.

PCI Express Interface (Primary Wi-Fi Data Path):

The E Key provides a single PCI Express Gen 3 (8.0 GT/s) lane. The transmit differential pair PETp0/PETn0 is on pins 35/37; the receive pair PERp0/PERn0 is on pins 41/43. Per the PCI Express M.2 Specification, AC coupling capacitors for the PCIe TX differential pair must be placed on the host (COM) side, while AC coupling capacitors for the PCIe RX differential pair must be placed on the M.2 add-in card side. This means the carrier board designer does not need to add AC coupling caps for the receive path — they are already on the module. The 100 MHz reference clock (REFCLKp0/REFCLKn0) is delivered from the host on pins 47/49 as a differential HCSL (High-Speed Current Steering Logic) pair with 0.7 V common-mode voltage and 800 mV peak-to-peak differential swing. PERST0# (pin 52) is an active-low reset from the host, and CLKREQ0# (pin 53) is an open-drain, active-low request from the module to enable the reference clock buffer. The host must provide a pull-up resistor on CLKREQ0#.

USB 2.0 Interface (Bluetooth HCI Transport):

The USB 2.0 differential pair is mandatory on E Key: USB_D+ on pin 3, USB_D- on pin 5, each terminated with 45-ohm nominal single-ended impedance (90-ohm differential). Every E Key-compliant host routes USB 2.0 to these pins. This is the transport layer used by virtually all Wi-Fi/BT combo modules for the Bluetooth Host Controller Interface (HCI). The Intel AX210, for instance, lists its system interface as “Wi-Fi (PCIe), BT (USB)” in the official datasheet — the Bluetooth controller is a separate USB device behind the integrated USB hub, enumerated as a dedicated Bluetooth radio by the operating system’s USB subsystem.

Intel CNVi (Connectivity Integration):

Intel’s proprietary CNVi (CNVio) bus uses E Key-specific pins for its Companion RF (CRF) modules. The CNVi interface comprises:

  • CNV_WR_CLK_DP/CNV_WR_CLK_DN (pins 23/21) — differential receive clock from CRF to PCH, 1.8 V signaling.
  • CNV_WR_LANE0_DP/CNV_WR_LANE0_DN (pins 17/15) — receive data lane 0.
  • CNV_WR_LANE1_DP/CNV_WR_LANE1_DN (pins 11/9) — receive data lane 1.
  • CNV_WT_CLK_DP/CNV_WT_CLK_DN (pins 73/71) — differential transmit clock from PCH to CRF.
  • CNV_WT_LANE0_DP/CNV_WT_LANE0_DN (pins 67/65) — transmit data lane 0.
  • CNV_WT_LANE1_DP/CNV_WT_LANE1_DN (pins 61/59) — transmit data lane 1.
  • CNV_BRI_DT/CNV_BRI_RSP (pins 36/22) — BRI bus (Bluetooth UART alternative, 1.8 V).
  • CNV_RGI_DT/CNV_RGI_RSP (pins 32/34) — RGI bus (radio general interface, used for CRF presence detection; platform requires a 20 k-ohm pull-up on RGI_DT).
  • CNV_RF_RESET_N (pin 10) — CRF reset, active low; requires a 75 k-ohm pull-down on the platform.
  • CNV_BT_I2C_SCLK/CNV_BT_I2S_SDO (pins 8/12) — Bluetooth I2C and I2S audio buses.
  • CNV_PA_BLANKING (pin 44) — coexistence blanking signal for WWAN/GNSS arbitration.

CRF modules (AX201, AX211, BE201) use the CNVi bus instead of PCIe+USB, which reduces BOM cost by eliminating the need for a discrete PCIe root port and USB host controller path for the Wi-Fi MAC and Bluetooth baseband. However, CNVi requires an Intel chipset (100 series or newer) that integrates the CNVi MAC. AMD platforms and older Intel chipsets do not support CNVi — they must use discrete PCIe+USB E Key modules (AX210, BE200).

Auxiliary Signals:

  • W_DISABLE1# (pin 56) and W_DISABLE2# (pin 54) — hardware RF kill inputs, active low, 3.3 V tolerant. When pulled low, the module must cease all RF transmission. W_DISABLE1# typically controls WLAN; W_DISABLE2# controls Bluetooth.
  • SUSCLK (pin 50) — 32.768 kHz suspend clock from the platform’s Real-Time Clock (RTC) domain, used for low-power idle wake-up.
  • PEWAKE0# (pin 55) — PCI Express wake signal, open-drain, active low, used by the module to assert a wake event from a low-power state (D3cold).
  • COEX_TXD/COEX_RXD/COEX3 (pins 48/46/44) — 3-wire coexistence interface for antenna sharing and transmission arbitration between WLAN and BT (and optionally LTE/WWAN). Signaling at 1.8 V.
  • UART TXD/RXD/CTS/RTS (pins 32/22/34/36) — general-purpose UART at 1.8 V, used for debug or secondary Bluetooth transport on select modules.
  • PCM_CLK/PCM_SYNC/PCM_IN/PCM_OUT (pins 8/10/12/14) — PCM/I2S digital audio interface for Bluetooth SCO (Synchronous Connection-Oriented) audio.
  • SDIO CLK/CMD/DATA[3:0] (pins 9/11/13/15/17/19) — SDIO 3.0 interface at 1.8 V, available on some E Key slots for modules that use SDIO instead of PCIe.
  • ALERT# (pin 62) — optional interrupt signal for platform management, 1.8 V.
  • I2C_CLK/I2C_DATA (pins 60/58) — I2C bus for platform management communication, 1.8 V.

Power is delivered at 3.3 V on pins 2, 4, 72, and 74. The specification limits maximum continuous current draw from the 3.3 V rail to 1.5 A for E Key modules (VCC_E), lower than the 3 A general M.2 limit for storage modules. The maximum insertion force is 20 N — 33% lower than the 30 N limit for B-Key and M-Key slots — reflecting the smaller form factor and more delicate RF components on wireless modules.

Current-generation E Key 2230 Wi-Fi modules include Intel AX210 (Wi-Fi 6E, Bluetooth 5.3, PCIe + USB), Intel BE200 (Wi-Fi 7, Bluetooth 5.4, PCIe + USB), Intel BE201 (Wi-Fi 7, Bluetooth 5.4, CNVi), Qualcomm QCNCM865 (FastConnect 7800, Wi-Fi 7, Bluetooth 5.4, PCIe + USB), and MediaTek MT7925 (Filogic 360, Wi-Fi 6E, Bluetooth 5.3, PCIe + USB). All share the same 60-pin, 2230, E Key edge connector with two IPEX MHF4 antenna ports.

What Is M.2 B+M Key WiFi Module

M.2 B+M Key (Socket 2 per PCI-SIG) combines the B Key notch (pins 12–19) and the M Key notch (pins 58–65), yielding a 67-active-pin edge connector with two physical cutouts. A B+M Key module can be physically inserted into any B Key-only, M Key-only, or B+M Key slot because the two notches align with both the B and M slot key walls. The standard form factors are 2242 (22 × 42 mm) and 2280 (22 × 80 mm), although 2230 B+M modules exist in limited quantities.

Host Interface Detection via CONFIG[3:0]:

A distinguishing feature of Socket 2 (B Key and B+M Key) is the CONFIG[3:0] pin set: CONFIG_3 on pin 1, CONFIG_0 on pin 21, CONFIG_1 on pin 69, and CONFIG_2 on pin 75. These four pins are strapped (pulled high or low) by the module to indicate to the host which protocol interface the module implements. The encoding follows the PCI-SIG-defined table:

  • 0000 — SATA SSD
  • 0100 — PCIe SSD
  • 0010 — WWAN, PCIe (Port Config 0)
  • 0110 — WWAN, PCIe (Port Config 1)
  • 0001 — WWAN, PCIe + USB 3.1 Gen 1 (Port Config 0)
  • 0101 — WWAN, PCIe + USB 3.1 Gen 1 (Port Config 1)
  • 0011 — WWAN, PCIe + USB 3.1 Gen 1 (Port Config 2)
  • 0111 — WWAN, PCIe + USB 3.1 Gen 1 (Port Config 3)
  • 1000 through 1110 — SSIC or vendor-defined configurations
  • 1111 — No module present (all straps high via pull-ups)

A B+M Wi-Fi module would need to set CONFIG[3:0] to one of the PCIe+USB configurations to make the host aware that USB 2.0/3.0 must be enabled for Bluetooth. However, most legacy B+M Wi-Fi modules did not implement CONFIG strap encoding correctly (or omitted it entirely), resulting in the host system not enabling the USB controller for the B+M slot — and consequently no Bluetooth.

PCI Express Interface on B+M Key:

B+M Key carries two PCIe lanes. Lane 0 uses PETp0/PETn0 on pins 47/49 (SATA-A+/A- alternate function) and PERp0/PERn0 on pins 41/43 (SATA-B+/B- alternate function). Lane 1 uses PETp1/PETn1 on pins 35/37 (USB 3.0 Tx alternate) and PERp1/PERn1 on pins 29/31 (USB 3.0 Rx alternate). The reference clock REFCLKp/REFCLKn is on pins 55/53, PERST# on pin 50, CLKREQ# on pin 52, and PEWAKE# on pin 54. Critically, the B+M Key PCIe signal set does not include a dedicated CLKREQ# open-drain handshake for each lane, and the PERST# is shared across all functions on the slot. This creates a power management ambiguity when a Wi-Fi module is placed in a B+M slot designed primarily for SSDs — the host may not implement PCIe ASPM (Active State Power Management) correctly for a wireless device on what it expects to be a storage slot.

USB Interface on B+M Key:

USB 2.0 D+/D- is available on pins 7/9. USB 3.0 (SSRX+/- on pins 29/31, SSTX+/- on pins 35/37) may be present on some B+M slots that follow the WWAN+USB3.1 configuration. However, the PCI-SIG specification does not mandate USB routing on B+M Key slots. On motherboards where the B+M slot is designed exclusively for SATA or PCIe NVMe SSDs, pins 7/9 are left as no-connects, and USB 3.0 pins are reassigned to the second PCIe lane. A Wi-Fi module relying on USB for Bluetooth will have no functional Bluetooth in such slots.

Known B+M Wi-Fi Modules:

The AzureWave AW-CB161 (Broadcom BCM94352Z, 802.11ac Wi-Fi 5, Bluetooth 4.1) was one of the more widely deployed B+M combo modules — shipped in select Dell Latitude E7470 and E5570 laptops. It used a 2230 form factor with B+M dual notches (a non-standard configuration for 2230), carried PCIe x1 for WLAN, and required USB on pins 7/9 for Bluetooth. The Intel Dual Band Wireless-AC 3165 also had a B+M Key SKU (3165NGW), which was a 2230 module with B+M notches — again, a mechanical anomaly since 2230 E Key is the Intel standard even for that chipset generation. Both modules are discontinued and unsupported in Windows 11 and recent Linux kernels.

As of Q2 2026, no B+M Key Wi-Fi module has been announced or produced for any standard beyond Wi-Fi 5. Intel, Qualcomm, and MediaTek have all ended B+M Key wireless development. The PCI-SIG M.2 specification itself has not defined a Wi-Fi-specific protocol configuration encoding in the CONFIG[3:0] table — the closest entries are WWAN PCIe+USB configurations, which are targeted at cellular modems, not WLAN.

Physical Pinout & Slot Notch Comparison

The following table provides a signal-group-level comparison. The E Key pin assignments are sourced from the PCI-SIG Socket 1 definition and cross-referenced with the Advantech AIMB-276 and Supermicro A4SAN-H E Key pin tables. The B+M Key assignments follow the PCI-SIG Socket 2 definition, with CONFIG[3:0] encoding per the Congatec AN43 application note:

Signal Group E Key (Socket 1) B+M Key (Socket 2)
Notch Position Pins 24–31 (single, center-right) Pins 12–19 + 58–65 (dual, left and right)
Active Pins 60 (of 75 positions) 67 (of 75 positions)
Standard Form Factor 2230 (22 × 30 mm); 1216 (12 × 16 mm) 2242, 2260, 2280 (22 mm × variable)
PCIe Lane Count 1 (x1), Gen 3 at 8 GT/s 2 (x2), Gen 3 at 8 GT/s per lane
PCIe Lane Mapping PETp0/n0: 35/37, PERp0/n0: 41/43, REFCLK: 47/49, PERST#: 52, CLKREQ#: 53, PEWAKE#: 55 L0: PETp0/n0: 49/47, PERp0/n0: 43/41. L1: PETp1/n1: 37/35, PERp1/n1: 31/29. REFCLK: 55/53, PERST#: 50, CLKREQ#: 52, PEWAKE#: 54
USB 2.0 Mandatory on pins 3 (D+), 5 (D-) Optional on pins 7 (D+), 9 (D-); not required by spec
USB 3.0 Not defined on E Key Optional, shared with PCIe Lane 1 on pins 29/31 (Rx) and 35/37 (Tx)
Host Interface Detection Not required; key type defines fixed interface CONFIG[3:0] on pins 1/21/69/75; 4-bit strap encoding for SATA/PCIe/WWAN
CNVi (Intel) Full support on pins 8–23, 32–38, 44–48, 59–73 Not supported
Coexistence Interface 3-wire COEX on pins 44/46/48 (1.8V); CNV_PA_BLANKING on pin 44; MFUART on pins 46/48 CNV_PA_BLANKING optional on pin 60; no standard 3-wire COEX pins
Antenna Connector IPEX MHF4 (I-PEX 20455), 2 ports, 9 GHz rated, 1.2 mm mating height U.FL or MHF1, 2 ports, ≤6 GHz rated, 2.5 mm mating height
3.3V Power Pins 2, 4, 72, 74; max 1.5 A (VCC_E) Pins 2, 4, 70, 72, 74; max 3 A (general M.2 limit)
RF Kill W_DISABLE1# pin 56, W_DISABLE2# pin 54; active-low, 3.3 V W_DISABLE1# pin 56, W_DISABLE2# pin 54; active-low, 3.3 V
Max Insertion Force 20 N (Socket 1 limit) 30 N (Socket 2 limit)

Antenna Connector Standards

The antenna interface is a critical but often overlooked compatibility factor. E Key modules shipping from the Wi-Fi 6 generation onward use the I-PEX MHF4 (I-PEX 20455 series) micro-coaxial connector, rated from DC to 9 GHz with a characteristic impedance of 50 ohms. The MHF4 has a mating height of 1.2 mm (from PCB surface to cable center) and a plug insertion force of 12 N maximum. The 9 GHz frequency rating is essential for Wi-Fi 6E and Wi-Fi 7 operation in the 6 GHz band (5.925–7.125 GHz), where legacy connectors exhibit increased return loss beyond 6 GHz.

Legacy B+M Key modules used the Hirose U.FL connector (also known as I-PEX MHF1), rated from DC to 6 GHz with a mating height of 2.5 mm. The U.FL has typical insertion loss of -0.3 dB at 3 GHz and -0.5 dB at 6 GHz; above 6 GHz, return loss degrades below -10 dB, making it unsuitable for 6 GHz Wi-Fi operation. The U.FL and MHF4 are not mechanically interchangeable — the MHF4 plug is smaller (2.0 mm × 2.0 mm ground pad vs. 3.2 mm × 3.2 mm for U.FL) and requires different mating adapter cables.

Some E Key modules from Intel’s 9xxx series and earlier (3165, 3168, 7265) used the U.FL connector, but the transition to MHF4 was essentially complete by 2018 (Intel 9560/9260 generation). All Intel AX200/AX210/BE200/BE201 modules use MHF4. Qualcomm QCNCM865 uses MHF4. MediaTek MT7921/MT7925 use MHF4. Adapter cables from U.FL to MHF4 exist but introduce approximately -0.5 dB to -1.0 dB of additional insertion loss per adapter pair, which directly reduces the maximum permissible path loss (MPPL) budget at the receiver sensitivity threshold.

Mating cycle specifications differ as well: U.FL is rated for 30 mating cycles, while MHF4 is rated for 50 cycles. Both connectors use a 0.81 mm diameter coaxial cable (typically 1.13 mm or 1.32 mm for low-loss variants).

Wi-Fi & Bluetooth Protocol Support by Key Type

E Key — Full Generational Coverage (Wi-Fi 4 through Wi-Fi 7):

E Key modules are available for every Wi-Fi generation from 802.11n (Wi-Fi 4) onward. The PCIe Gen 3 x1 lane provides 984 MB/s unidirectional bandwidth, which far exceeds the peak PHY rate of any current Wi-Fi standard (Wi-Fi 7’s 5.8 Gbps per stream is 725 MB/s; a single PCIe Gen 3 lane provides a 36% margin above that). The USB 2.0 interface on pins 3/5 delivers 480 Mbps theoretical throughput — well above Bluetooth 5.x BR/EDR (3 Mbps) and LE (2 Mbps) data rates. This headroom ensures that even with simultaneous Wi-Fi and BT operation, neither interface becomes the bottleneck.

Current-generation E Key modules support:

  • Intel AX210 — Wi-Fi 6E (802.11ax), 2×2:2, 160 MHz, 2.4/5/6 GHz, Bluetooth 5.3; PCIe + USB; Linux iwlwifi support since kernel 5.10+
  • Intel BE200 — Wi-Fi 7 (802.11be), 2×2:2, 320 MHz, 2.4/5/6 GHz, Bluetooth 5.4; PCIe + USB; Linux iwlwifi support since kernel 6.2+
  • Intel BE201 — Wi-Fi 7, 2×2:2, 320 MHz, Bluetooth 5.4; CNVi-only, requires Intel chipset with integrated CNVi MAC (12th Gen Core or newer)
  • Qualcomm QCNCM865 — Wi-Fi 7 (FastConnect 7800), 2×2:2, 320 MHz, Bluetooth 5.4; PCIe + USB
  • MediaTek MT7925 — Wi-Fi 6E (Filogic 360), 2×2:2, 160 MHz, Bluetooth 5.3; PCIe + USB

B+M Key — Limited to Wi-Fi 5 (802.11ac):

B+M Key Wi-Fi modules top out at 802.11ac Wave 2 (Wi-Fi 5). The Broadcom BCM94352Z (AzureWave AW-CB161) supports 2×2:2 at 80 MHz, delivering up to 867 Mbps PHY rate on 5 GHz and 300 Mbps on 2.4 GHz, with Bluetooth 4.1. The Intel 3165NGW supports 1×1:1 at 80 MHz (433 Mbps PHY rate) with Bluetooth 4.2. Neither module supports 160 MHz channel width, 1024-QAM modulation, OFDMA, or any Wi-Fi 6 (802.11ax) features.

The fundamental limitation is not the PCIe lane bandwidth (PCIe Gen 2 x1 at 5 GT/s is sufficient for Wi-Fi 5), but rather the lack of USB routing mandate in the B+M Key specification. Without guaranteed USB 2.0 on pins 7/9, Bluetooth cannot operate reliably across different host platforms. Additionally, the CONFIG[3:0] detection mechanism has no standard encoding for “Wi-Fi module present,” causing BIOS/UEFI to misconfigure the slot’s power management and hot-plug capabilities.

The Wi-Fi 5 vs Wi-Fi 6E/7 gap translates to real-world throughput differences: a B+M Broadcom BCM94352Z in 5 GHz 80 MHz delivers ~400 Mbps TCP throughput, while an E Key Intel AX210 at 160 MHz 6 GHz delivers ~1.6 Gbps TCP throughput — a 4× improvement. In the 2.4 GHz band, the gap is even larger due to OFDMA and MU-MIMO support in Wi-Fi 6 that B+M modules lack entirely.

M.2 Key Compatibility — Can You Fit E Key Into B+M Slot?

Physical impossibility: the notch does not permit it.

An E Key module has its notch at pins 24–31. A B+M Key slot has its first notch at pins 12–19 and its second notch at pins 58–65. When attempting to insert an E Key module into a B+M slot, the E Key module’s continuous (un-notched) edge at pins 12–19 collides with the slot’s key wall at the same position. The plastic key wall in the slot physically blocks insertion. Conversely, a B+M Key module has its first notch at 12–19 — the region where an E Key slot is solid, un-notched plastic — so the B+M module will not seat in an E Key slot either.

Adapter cards exist — with signal integrity caveats:

M.2 Key adapters (e.g., E Key to B+M Key, E Key to M Key PCIe x4) are available from third-party vendors, but they operate by routing the E Key module’s PCIe lane through additional PCB traces, a second M.2 connector pair, and often a PCIe switch or redriver IC. Each additional interconnect introduces insertion loss: a single M.2 connector pair adds approximately 0.3–0.5 dB of insertion loss at 8 GHz (PCIe Gen 3). A typical adapter adds 1–2 dB total insertion loss, which is tolerable for PCIe Gen 3 but becomes marginal for PCIe Gen 4 or Gen 5 signaling.

Beyond signal integrity, adapter use raises three issues:

  • Antenna routing: The adapter moves the module away from the chassis-embedded antenna connectors. Short U.FL-to-MHF4 adapter cables (typically 50–100 mm) are needed, adding the -0.5 to -1.0 dB insertion loss noted above.
  • BIOS whitelist: Many OEM platforms (Lenovo, Dell, HP) implement a BIOS-embedded PCIe subsystem Vendor ID/Device ID (SVID/SDID) whitelist. An unauthorized module causes the system to abort initialization at the Option ROM loading phase, resulting in “Unsupported wireless card” or “Unauthorized network card detected” POST error. Whitelist bypass requires either modified BIOS firmware (SPI flash programming via SOIC-8 clip) or nvramtool (Lenovo-only, requires physical access to the EC flash).
  • CNVi loss: If the E Key module requires CNVi (BE201), an adapter cannot provide CNVi connectivity — CNVi uses non-PCIe pins (CNV_WT_CLK on 73/71, CNV_RGI_DT on 32, etc.) that an adapter bridging PCIe-only traces cannot forward. The module will not be detected.

Device Applicability — Which Key Type Supports Which Device

E Key (Socket 1) is the standard for all modern Wi-Fi/BT combo wireless modules. Laptops, ultrabooks, mini-PCs, industrial embedded systems, and single-board computers from 2016 onward use E Key 2230 slots for wireless connectivity. Examples by platform:

  • Consumer laptops (Intel Evo, AMD Ryzen): Dell XPS 13/15/17, Lenovo ThinkPad X1 Carbon (Gen 8+), ThinkPad T14s, HP EliteBook 840/860 — all use E Key 2230 for Wi-Fi 6E/7 modules.
  • Mini-PCs: Intel NUC 12/13 (E Key 2230), ASUS PN64, Minisforum UM790 Pro — E Key slot populated with AX210 or MediaTek MT7925.
  • Industrial embedded: Advantech AIMB-276 (Mini-ITX, LGA1700) — full E Key pinout per PCI-SIG Socket 1, including CNVi for Intel CRF modules. Supermicro A4SAN-H (A4SAN-H) — E Key connector with USB_D+/D- on pins 3/5, CNV_WR_CLK/DP on pins 23/21, CNV_WT_CLK_DP on pin 73, PERST0# on pin 52, CLKREQ0# on pin 53.
  • Single-board computers: Raspberry Pi 5 (Broadcom BCM2712) — no M.2 connector directly; HatDrive! boards break out PCIe Gen 3 x1 to E Key 2230 slot via the 16-pin PCIe FPC connector (SFF-8654).

B+M Key (Socket 2) is designed for storage and WWAN — not Wi-Fi. Instances where B+M Wi-Fi modules shipped:

  • Dell Latitude E7470 / E5570 (2015–2017): AzureWave AW-CB161 (BCM94352Z) B+M 2230. Dell stopped using B+M Wi-Fi after the Latitude 7000 series’ 2018 redesign.
  • Lenovo ThinkPad T450 / T460 / X250: Intel 3165NGW B+M 2230. Lenovo switched to E Key starting with the T470/X270 generation.
  • HP ProBook 450 G3 / 470 G3: Intel 3165NGW B+M 2230. HP transitioned to E Key from the G4 generation onward.
  • Desktop adapter cards (legacy only): Some PCIe x1 to M.2 B+M Key adapter cards with external antenna brackets shipped with BCM94352Z modules for desktop builds. These are discontinued.

If you are building or upgrading a system in 2026, only E Key is relevant. No current-generation Wi-Fi chipset vendor offers a B+M Key SKU. Upgrading a B+M-equipped laptop from 2015–2017 to a modern Wi-Fi 6E module requires either a motherboard replacement or an adapter solution — with the caveats noted above regarding BIOS whitelists, antenna connector mismatch, and Bluetooth USB routing.

Selection Guidelines

When selecting an M.2 Wi-Fi module for a given platform, use the following decision criteria in order:

  1. Verify the M.2 slot key type. Physically inspect the slot for the notch positions, or consult the platform’s technical manual. A single notch at pins 24–31 = E Key (Socket 1). Dual notches at pins 12–19 and 58–65 = B+M Key (Socket 2). If using an adapter, ensure the host slot is Key B or Key M (not Key E-only).
  2. Verify the PCIe generation and lane count available at the slot. An E Key slot on an Intel 300-series chipset (Coffee Lake) provides PCIe Gen 3 x1 from the PCH root port. An E Key slot on an AMD B550 chipset provides PCIe Gen 3 x1 from the chipset. An E Key slot directly connected to a CPU’s PCIe root port (e.g., on a NUC or embedded board) may support Gen 4 x1 — but no current Wi-Fi module requires Gen 4 bandwidth.
  3. Verify USB 2.0 routing. For E Key, USB is mandatory — confirmed. For B+M Key, check the platform BIOS or schematic to confirm that USB_D+/D- is connected to pins 7/9. On many B+M slots, these pins are NC unless the slot is configured for WWAN+USB operation.
  4. Check antenna connector type. If upgrading to an E Key Wi-Fi 6E/7 module, confirm that the chassis antenna cables use MHF4 plugs. If they use U.FL plugs, adapter cables are required — and the insertion loss penalty must be accounted for in the link budget.
  5. Check BIOS whitelist compatibility. For OEM laptops (Lenovo, Dell, HP), verify that the target module’s PCIe SVID/SDID (e.g., Intel AX210: VID 8086, DID 2725, SUBSYS 00248086) is present in the BIOS whitelist. If not, a BIOS modification or hardware programmer (CH341A with SOIC-8 clip) may be needed.
  6. For Intel platforms only: decide between PCIe+USB and CNVi modules. If the chipset supports CNVi (Intel 100 series or newer, with appropriate PCH firmware) and the E Key slot routes the CNVi differential pairs (pins 9/11/15/17/21/23/59/61/65/67/71/73), a CRF module (BE201) saves one PCIe lane. Otherwise, a discrete PCIe+USB module (BE200, AX210) is required.

Summary: Decision Flowchart

1. Does your platform have an M.2 slot?
├─ Yes → Go to 2
└─ No → Use PCIe x1 or USB adapter for external M.2

2. What key type is the slot?
├─ E Key (notch 24–31) → Go to 3
├─ B+M Key (notches 12–19 & 58–65) → Go to 5
└─ Unknown → Inspect notch positions physically

3. Does the platform use an Intel chipset with CNVi?
├─ Yes (Intel 100-series or newer PCH) → Go to 4
└─ No (AMD, older Intel, or CNVi not routed) → Choose PCIe+USB E Key module:
├─ Wi-Fi 7 needed? → Intel BE200 or Qualcomm QCNCM865
├─ Wi-Fi 6E sufficient? → Intel AX210 or MediaTek MT7925
└─ Budget Wi-Fi 6? → Intel AX200 (Wi-Fi 6, BT 5.2)

4. CRF (CNVi) module or discrete?
├─ CRF module → Intel BE201 (Wi-Fi 7) or AX211 (Wi-Fi 6E)
├─ Confirm BIOS has CRF support enabled
└─ Confirm CNVi differential pairs are routed (pins 9-73)

5. B+M Key slot — Wi-Fi upgrade options:
├─ Can you replace the motherboard? → Choose one with E Key slot
├─ Will an adapter work physically? → Use E Key to B+M adapter:
│ ├─ Verify BIOS will not block by SVID/SDID whitelist
│ ├─ Account for PCIe Gen 3 insertion loss (1-2 dB per adapter)
│ └─ Account for MHF4-to-U.FL adapter antenna loss (0.5-1.0 dB)
└─ If any check fails → Keep existing B+M Wi-Fi 5 module or use USB Wi-Fi

For a full comparison of all WiFi module interface options, refer to the WiFi Module Complete Guide: WiFi 5 to WiFi 7, Form Factors, Chipsets & Selection.

Frequently Asked Questions

1. Can I physically insert an M.2 E Key WiFi module into a B+M Key slot?

No. The E Key notch at pins 24–31 is incompatible with the B+M Key dual notch at pins 12–19 and 58–65. The solid edge of the E Key module at pins 12–19 collides with the B+M slot key wall. Adapter PCBs exist but add insertion loss and cannot forward CNVi signals.

2. Why do B+M Key WiFi modules exist if the specification was designed for storage?

B+M Key provided mechanical compatibility with both B-only and M-only slots, allowing OEMs to use a single module SKU across different motherboard designs. However, the PCI-SIG Socket 2 specification was never formally extended to define a Wi-Fi-specific CONFIG[3:0] encoding. B+M Wi-Fi modules were implemented by Broadcom and Intel as semi-proprietary workarounds and were abandoned after Wi-Fi 5 due to the complexities of Bluetooth USB routing and power management.

3. Does an M.2 E Key WiFi module support Bluetooth?

Yes, because the E Key specification mandates USB 2.0 routing on pins 3/5. The Bluetooth HCI transport runs over USB. Every E Key Wi-Fi/BT combo module uses this path. In contrast, a B+M Key module’s Bluetooth may not work unless the host platform explicitly routes USB to pins 7/9, which is not required by the specification.

4. What is the maximum power consumption of E Key versus B+M Key WiFi modules?

Per the PCI-SIG M.2 specification, E Key modules are limited to 1.5 A at 3.3 V (5.0 W). B+M Key modules can draw up to 3 A at 3.3 V (10 W), though actual Wi-Fi module power stays under 3 W for both types in active TX mode (Intel AX210: 2.5 W peak at 2×2 160 MHz). The 1.5 A limit on E Key is not the binding constraint — thermal dissipation in the 2230 form factor is the real limitation.

5. Can I use an M.2 E Key WiFi module in an M.2 M Key NVMe slot?

Physically, the E Key module’s notch at 24–31 does not align with the M Key notch at 58–65 — the M Key slot’s key wall at pins 24–31 will block insertion. Adapter cards (E Key to M Key) exist and are used on desktop PCs that have spare M Key M.2 slots. The adapter bridges the single PCIe Gen 3 lane from the E Key module to one of the M Key slot’s four PCIe lanes. The module is enumerated as a PCIe device on the M Key slot’s root port. Bluetooth requires USB routing, which the adapter must provide via a separate USB cable from a motherboard USB 2.0 header to the adapter.

6. Why do modern WiFi modules use IPEX MHF4 instead of U.FL?

MHF4 is rated to 9 GHz, while U.FL is specified only to 6 GHz. Wi-Fi 6E and Wi-Fi 7 operate in the 6 GHz band (5.925–7.125 GHz), where U.FL return loss degrades below -10 dB. MHF4 also has a lower profile (1.2 mm vs 2.5 mm mating height), which helps thin laptop designs. The smaller footprint (2.0 mm × 2.0 mm ground pad vs 3.2 mm × 3.2 mm) saves PCB area near the edge connector.

7. Can I replace a soldered-down WiFi module with an M.2 E Key module?

Soldered-down (1216 or BGA) Wi-Fi modules use the same CNVi or PCIe+USB electrical interface but are mounted directly on the motherboard PCB. There is no M.2 connector. Replacement requires hot-air rework to desolder the old component and re-solder a new one — assuming the new component is footprint-compatible and the BIOS has the appropriate firmware support. This is not a user-serviceable operation. Some motherboards (e.g., Framework Laptop 13) provide both a soldered-down CRF module and an M.2 E Key expansion slot, but that is exceptional.

8. What is the CONFIG[3:0] encoding on B+M Key and how does it affect WiFi?

CONFIG[3:0] is a 4-bit strap that tells the host which protocol the B+M Key slot should use. The pins are located at positions 1 (CONFIG_3), 21 (CONFIG_0), 69 (CONFIG_1), and 75 (CONFIG_2). A module that does not set these straps correctly will cause the host to initialize the wrong interface (e.g., SATA instead of PCIe+USB). For Wi-Fi, the module should assert CONFIG[3:0] = 0001, 0101, 0011, or 0111 (WWAN + PCIe + USB 3.1 configurations), but legacy B+M Wi-Fi modules often omitted proper strapping, leading to Bluetooth non-functional on many platforms.

9. Are there WiFi 7 modules available in B+M Key?

No. As of Q2 2026, no Wi-Fi 7 chipset vendor (Intel, Qualcomm, MediaTek, Broadcom) has announced or produced a B+M Key module. All Wi-Fi 7 M.2 modules are E Key 2230. The PCI-SIG M.2 specification has not defined a Wi-Fi 7 protocol configuration for Socket 2, and there is no industry demand for B+M Key wireless at the Wi-Fi 7 performance level.

10. How can I identify whether my laptop is using an E Key or B+M Key WiFi module?

Three methods: (a) remove the module and inspect the edge connector notch — a single notch near the center-right (pins 24–31) is E Key, two notches near the ends are B+M; (b) check the module’s part number — if it ends in “NGW” (Intel) or “CB1″ (AzureWave), search the datasheet for key type; (c) check the PCIe subsystem ID from the operating system — on Linux, run ‘lspci -vv -s $(lspci | grep Network | cut -d” ” -f1)’ and check the “Subsystem” field; on Windows, look in Device Manager under “Network adapters” > Properties > Details > Hardware IDs. If the module is from 2018 or later, it is almost certainly E Key.

References

  1. PCI Express M.2 Specification Revision 3.0, Version 1.2 — PCI-SIG, June 26, 2019. Defines 75-position edge connector, key types, signal assignments, socket classifications, and mechanical dimensions for all M.2 form factors.
  2. Intel Wi-Fi 6E AX210 Product Specifications — Intel Corporation, 2022. Documents PCIe + USB interface, 2×2:2 antenna configuration, MHF4 connector type, 2230 form factor, and Bluetooth 5.3 support.
  3. Intel 600 Series Chipset Platform Controller Hub (PCH) Datasheet — Intel Corporation, Doc #631913, 2023. Defines CNVi pin assignments, signal voltage levels (1.8V), CRF programming sequences, and CNV_RF_RESET_N 75 k-ohm pull-down requirement.
  4. Supermicro A4SAN-H Motherboard M.2 Connector Pin Definitions — Super Micro Computer, Inc. Real-world E Key pinout implementation showing USB_D+/-, CNV_WR_CLK, CNV_WT_CLK, PERST0#, CLKREQ0#, PEWAKE0#, and CNV_RF_RESET_N signal assignments.
  5. Congatec Application Note AN43: M.2 Module Connector — congatec AG, 2022. Provides PCI-SIG-compliant pinout tables for E Key and B Key, PCIe AC coupling capacitor placement rules (TX on carrier, RX on module), CLKREQ# open-drain pull-up design guidance, and CONFIG[3:0] encoding methodology for Socket 2.

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