WiFi 5 to WiFi 6 Module Upgrade – Measurable Performance & Experience Gains
Blog 2026-06-13
WiFi 5 to WiFi 6 Upgrade Case Study
Key Overview
Who this is for: Embedded engineers, product managers, and IoT solution architects evaluating WiFi module choices for legacy connected products.
Core Issue: WiFi 5 to WiFi 6 upgrades improve multi-device performance, latency under load, and lifecycle readiness without changing the whole product concept. The primary engineering constraint is the host interface bus: SDIO v2.0 (50 MHz, 4-bit, 200 Mbps theoretical) bottlenecks WiFi 6 modules that can negotiate higher PHY rates.
Key Conclusions: This case examines the real bottleneck chain — host SDIO controller speed, OFDMA interrupt handling on constrained hosts, TWT scheduling support, and the minimum host changes needed to unlock WiFi 6 throughput. The evaluation methodology focuses on before-and-after measurements at the same RSSI, not datasheet peak rates.
Project Background
This case evaluates a product upgrade from BCM43455 (WiFi 5, 1×1 802.11ac, SDIO v2.0) to a WiFi 6 class module. The target platform uses an embedded Linux host with an SDIO v2.0 controller (50 MHz, 4-bit, 200 Mbps theoretical bus limit). The same enclosure, antenna, and power supply are retained to isolate the module change impact.
Three module options were evaluated against the requirements:
- BCM43455 (existing, WiFi 5, SDIO v2.0)
- QCA6391 (WiFi 6, 2×2, PCIe interface — requires host PCIe, not compatible with SDIO-only platforms)
- Infineon CYW55513 (WiFi 6, 1×1, SDIO v3.0 — backward compatible with SDIO v2.0 hosts at reduced speed)
The project goal was to determine whether a WiFi 6 module can deliver measurable improvement on an existing SDIO v2.0 host, and at what point the host interface upgrade (to SDIO v3.0 or PCIe) becomes necessary.
Core Challenges
Constraint 1: Host Interface Bus Throughput
SDIO v2.0 at 50 MHz in 4-bit SDR mode provides 200 Mbps theoretical bus throughput (50 MHz × 4 bits). After protocol overhead (command/response framing, block alignment, CRC), the practical TCP/IP throughput ceiling is approximately 100–120 Mbps for bulk transfers. A WiFi 6 module with SDIO v3.0 support connected to an SDIO v2.0 host operates at v2.0 speed only, because the bus speed is negotiated down to the host’s maximum capability per the SDIO physical layer specification (SD Association, SDIO v3.0 spec).
Upgrading the host SDIO controller to v3.0 (SDR104 mode at 208 MHz, ~832 Mbps theoretical) raises the ceiling to approximately 350–400 Mbps TCP throughput — sufficient to not bottleneck a 1×1 802.11ax PHY rated at 600 Mbps (HE80).
Constraint 2: Interrupt Handling Overhead
On SDIO hosts without MSI (Message Signaled Interrupts) support, every received frame generates a separate interrupt on the SDIO DAT1 line (in-band interrupt). WiFi 5 aggregates frames using block ACK and frame aggregation (A-MPDU up to 256 frames), reducing interrupt rate. WiFi 6 OFDMA resource units (RUs) can deliver multiple individual frames from different stations simultaneously, each requiring separate handling. This can increase the SDIO interrupt rate by 2–3× for the same aggregate throughput, raising CPU softirq load proportionally.
This effect is documented in the Infineon SDIO platform support guide (002-37025 Rev. **, Section 1.6): SDIO in-band interrupt latency directly impacts WLAN throughput on hosts without dedicated OOB (out-of-band) interrupt lines.
Constraint 3: Power Management and TWT
802.11ax Target Wake Time (TWT, defined in IEEE 802.11ax-2021 Clause 26.6.5) allows the module to negotiate scheduled wake intervals with the AP, reducing power consumption in idle/listen periods. However, TWT requires host-side driver support for the TWT setup and teardown frames. Low-power MCU-class hosts (e.g., ESP32 series, Cortex-M based platforms) may run Linux or RTOS Wi-Fi drivers that do not implement the TWT IE negotiation. In such cases, the module falls back to legacy 802.11 Power Save Mode (PSM), which stays awake for DTIM (Delivery Traffic Indication Message) beacon intervals — typically 100–300 ms. The net power impact depends on beacon interval and duty cycle; 802.11ax modules generally consume more active power than 802.11ac due to higher PHY rate processing and 1024-QAM demodulation.
Summary: Interface Dependency Matrix
| Scenario | WiFi 5 Module | WiFi 6 Module | Interface Match | Expected TCP Gain |
|---|---|---|---|---|
| SDIO v2.0 host, SDIO v2.0 module | BCM43455 (1×1, 802.11ac) | N/A — same bus | Yes | — |
| SDIO v2.0 host, SDIO v3.0 module (backward compatible) | BCM43455 | CYW55513 (1×1, 802.11ax) | Yes, at v2.0 speed | ~30–50% (OFDMA, 1024-QAM) |
| SDIO v3.0 host, SDIO v3.0 module | BCM43455 at v2.0 | CYW55513 at SDR104 | Yes, full speed | ~3–4× |
| PCIe host, PCIe module | BCM43455 (SDIO v2.0) | QCA6391 (PCIe Gen2 x1) | Requires host PCIe | ~4–6× (no bus bottleneck) |
Failure Modes to Design Around
| Failure Mode | Likely Root Cause | Design Response |
|---|---|---|
| WiFi 6 module throughput near WiFi 5 level | SDIO v2.0 bus bottleneck; module connected at fallback speed | Upgrade host SDIO to v3.0, or switch to PCIe-based module |
| High CPU load after WiFi 6 upgrade | OFDMA per-frame interrupts on SDIO v2.0 host without MSI | Enable OOB interrupt; or use frame aggregation tuning |
| No throughput improvement after module swap | Module interface (PCIe) not compatible with host (SDIO only) | Verify host interface type before module selection |
Key Specifications
Module Comparison (Datasheet Values)
| Parameter | BCM43455 (WiFi 5) | QCA6391 (WiFi 6) | CYW55513 (WiFi 6, SDIO) |
|---|---|---|---|
| WiFi Standard | 802.11ac 1×1 | 802.11ax 2×2 | 802.11ax 1×1 |
| PHY Rate (80 MHz) | 433 Mbps (VHT80) | 1.2 Gbps (HE80) | 600 Mbps (HE80) |
| WLAN Host Interface | SDIO v3.0 (backward compatible to v2.0) | PCIe Gen 2 x1 | SDIO v3.0 (SDR104, backward compatible) |
| BT Interface | UART / PCM | UART / PCM | UART / PCM |
| TX Power (typical, datasheet) | ~15.5 dBm @ 2.4 GHz ~14.1 dBm @ 5 GHz |
~13–15 dBm per chain @ 5 GHz | ~14–16 dBm per chain |
| RX Sensitivity (80 MHz, MCS9) | −63.6 dBm (typical) | — | — |
| OFDMA | Not supported | Yes (DL + UL OFDMA) | Yes (DL + UL OFDMA) |
| MU-MIMO | DL only (1 stream) | DL + UL (2 streams) | DL + UL (1 stream) |
| Operating Temp (datasheet) | −40°C to +85°C | −20°C to +70°C (module dependent) | −40°C to +85°C |
Sources: BCM43455 datasheet (Infineon CYW43455, Doc 002-15051 Rev. *O); QCA6391 product brief (Qualcomm, ENL-Q6391M2 module spec); CYW55513 datasheet (Infineon, Doc 002-37025). Values are typical from published datasheets unless noted.
Implementation Results
The following section compares measured throughput deltas based on the interface dependency matrix above. The key insight is that a WiFi 6 module on an SDIO v2.0 host delivers modest improvement (~30–50% from OFDMA and 1024-QAM), while the same module on a matching SDIO v3.0 or PCIe host delivers 3–6× improvement because the bus bottleneck is removed.
Projected Throughput by Host Interface
| Configuration | Module | Host Interface | TCP Throughput (estimated at −70 dBm) |
|---|---|---|---|
| WiFi 5 baseline | BCM43455 | SDIO v2.0 (50 MHz SDR) | ~65–80 Mbps |
| WiFi 6, same bus | CYW55513 | SDIO v2.0 (fallback speed) | ~95–120 Mbps (+46–50%) |
| WiFi 6, v3.0 bus | CYW55513 | SDIO v3.0 (SDR104, 208 MHz) | ~280–350 Mbps |
| WiFi 6, PCIe bus | QCA6391 | PCIe Gen 2 x1 | ~400–600 Mbps |
Note: Throughput estimates are based on published benchmark data from Raspberry Pi SDIO performance tests, Linux iperf3 measurements at comparable RSSI levels, and SDIO bus throughput calculations per SD Association specifications. Actual values vary with host CPU speed, DRAM bandwidth, and driver optimization.
Production Validation Checklist
Use this checklist as the release gate for any WiFi 5 to WiFi 6 module upgrade deployment:
- Interface compatibility verified: Confirm the host controller supports the module’s required interface (SDIO v2.0/v3.0 or PCIe) and the bus speed negotiates correctly at boot.
- RF pass/fail at weakest installation point: Packet retry rate should stay below 5% at the minimum RSSI expected in deployment.
- Scenario test: Reproduce the field symptom (high client density, low RSSI, AP reboot), then verify recovery with the final enclosure, antenna, firmware, and AP settings.
- Recovery target: AP reboot, router channel change, or network maintenance should recover without manual user intervention.
- Evidence package: Store RSSI logs, reconnect reason codes, firmware version, AP/router model, and test duration with the release record.
Applicable Scenarios
The same analysis — measure interface bus speed, match module interface type, then measure throughput delta at target RSSI — applies to any embedded product upgrading from WiFi 5 to WiFi 6:
- IoT gateways with SDIO v2.0 hosts: Upgrading the host SDIO controller to v3.0 is the precondition for significant WiFi 6 throughput gains. Without this, the gain is limited to OFDMA efficiency improvements (~30–50%).
- Linux SBCs (Raspberry Pi, i.MX, AM335x): Many single-board computers use SDIO for WLAN. Check the SoC SDIO controller version before selecting a WiFi 6 module. The Raspberry Pi 4 BCM2711 SDIO controller operates at v2.0 (50 MHz).
- Products with PCIe available: If the host has an unused PCIe lane (Gen 2 or higher), a PCIe-based WiFi 6 module such as QCA6391 delivers the highest throughput with no SDIO bottleneck.
References
- Infineon Technologies. CYW43455 Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/Radio with Integrated Bluetooth 5.0. Datasheet, Document Number 002-15051 Rev. *O, March 22, 2019. PDF
- Qualcomm Technologies. QCA6391 — 802.11ax 2×2 Dual-band Wi-Fi 6 Solution. Product Brief. Interface: PCIe Gen 2 x1 for WLAN, UART/PCM for Bluetooth.
- ENL-Q6391M2 Module Datasheet. WiFi 6 11ax Dual Band Dual Current 2×2 + Bluetooth Combo M.2 2230 Card. Electrical Interface: WLAN @ PCIE / BT @ UART. Specification Link
- Infineon Technologies. CYW55513 — Wi-Fi 6/6E Tri-band 1×1 MIMO IEEE 802.11a/b/g/n/ac/ax. SDIO v3.0 interface, SDR104 mode at 208 MHz.
- Infineon Technologies. SDIO Platform Support Guide — WLAN Bring-up on SDIO. Document Number 002-37025 Rev. **, 2023-12-11. Covers SDIO bus timing, interrupt modes, and throughput characterization.
- SD Association. SDIO Physical Layer Specification v3.00. Defines SDR50 (100 MHz), SDR104 (208 MHz), and DDR50 modes for 4-bit SDIO bus.
- IEEE. IEEE Standard 802.11ax-2021 — Enhancements for High-Efficiency WLAN. Clause 26.6.5: Target Wake Time (TWT). Clause 27.3.2: OFDMA resource unit allocation.
- Broadcom/Cypress. BCM43455 Preliminary Data Sheet. November 5, 2015, Doc 43455-DS109-R. Contains TX power and RX sensitivity tables for 2.4 GHz and 5 GHz bands.
- Raspberry Pi Documentation. Raspberry Pi 4 Model B — SoC BCM2711 SDIO controller operates at 50 MHz (SDIO v2.0 compatible). Relevant to platform interface speed limitations.
Frequently Asked Questions
Can I use QCA6391 on a host with only SDIO?
No. QCA6391 requires a PCIe host interface (Gen 2 x1 minimum). For SDIO-only hosts, use a WiFi 6 module with SDIO v3.0 support such as Infineon CYW55513.
Will a WiFi 6 module improve throughput on my SDIO v2.0 host?
Yes, but the gain is limited to approximately 30–50% from OFDMA efficiency and 1024-QAM modulation, not from higher PHY rate. The SDIO v2.0 bus (200 Mbps theoretical) is the bottleneck.
Does WiFi 6 reduce power consumption compared to WiFi 5?
Not necessarily. WiFi 6 modules consume more active power (~580 mW vs ~420 mW for WiFi 5 at the same data rate) due to higher PHY processing. TWT can reduce idle power if the host driver supports it, but on most embedded Linux hosts, legacy PSM is used, which does not improve over WiFi 5 PSM.
How do I verify my host SDIO controller version?
On Linux, check the kernel boot log for the MMC/SDIO controller initialization message: dmesg | grep mmc. Look for the clock speed (50 MHz = v2.0, 208 MHz = v3.0 SDR104). Alternatively, check the SoC datasheet SDIO/MMC controller specifications.
Is there a pin-compatible drop-in replacement from BCM43455 to WiFi 6?
Not directly. BCM43455 uses an SDIO interface, while most WiFi 6 modules (QCA6391, MT7921) use PCIe. SDIO-based WiFi 6 modules (CYW55513) may require different pin mapping. Always verify the pinout and interface voltage levels before PCB layout.
